Phased-array antennas and digital beamforming are key technologies that will boost the performance of future spaceborne radar imaging and broadband satellite communication systems. Digital beamforming, unlike analog beamforming, typically requires a set of data converters per antenna element. These converters need clocks with a specific defined phase relationship. This reference design shows how to generate low noise megahertz to gigahertz clock signals with defined and adjustable phase relationship. Clock phase even recovery is possible after single event strikes. JESD204B support is shown by operating two ADC12DJ3200QML-SP evaluation modules with their corresponding FPGA-based capturing platforms at 3.2 GHz with 10-ps board-to-board skew.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | Space-Grade, Multichannel, JESD204B 15-GHz Clock Reference Design | PDF | HTML | Mar. 21, 2023 |
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