Clocks & timing
Build your system using high-performance clocking solutions with our BAW technology
Tap into the infinite potential of bulk acoustic wave (BAW), fractional output divider and radiation-hardened technologies by using our clocking solutions to meet your needs for enterprise, telecommunications, automotive, industrial, test and measurement, and aerospace and defense applications. Surpass jitter requirements, improve system performance with our BAW clocking solutions, and create products that can endure extreme environmental conditions.
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BAW resonator technology
Bulk acoustic wave (BAW) is a resonator technology that uses piezoelectric transduction to generate a gigahertz frequency.
Design & development resources
Design tool
Clock tree architect programming software
Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Application software & framework
Texas Instruments Clocks and Synthesizers (TICS) Pro Software
Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Application software & framework
Texas Instruments PLLatinum Simulator Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
Why choose our clocks & timing portfolio?
Innovative technology
Our clocking products utilize integrated BAW resonator technology, advanced CMOS and SiGe processes, all manufactured at TI factories.
Built for reliability
BAW technology enables high resiliency to harsh environmental conditions such as mechnical shock and vibration and achieves 100x better MTBF compared to quartz based solutions.
Broad portfolio
Our clocking portfolio offers multisource and high performance solutions for enterprise, telecom, broad industrial, test and measurement, defense and aerospace leveraging 60+ years of space expertise.
Dedicated design tools and resources
Simplify your design process using our Clock Tree Architect, PLLatinum Simulator, and TICS Pro tools to select, simulate performance, and program our clocking products.
Clocking application standard trends
Network synchronizers with BAW VCO for wireless and Ethernet-based networking applications
TI’s network synchronizers are designed to meet the stringent jitter cleaning, wander attenuation, reference clock generation, and hitless switching. IEEE-1588v2 Precision Time Protocol (PTP) software stack, servo loop, device drivers, source code, and optional firmware are provided along with the hardware solution.
- Targeted for wired and wireless networking. 56G/112G/224G PAM-4 SerDes for ethernet-based networking, 4G/5G macro, AAS, RRU, BBU core modules and small cell wireless communications.
- Industry leading timing accuracies and compliance. Full timing support, 1PPS signal deviation is far less than +/-5 ns. Partial timing support, less than +/- 1µs with PDVs in excess of 230µs. Compliant for PTP telecom profiles G8275.1 and G.8275.2.
Application note
ITU-T G.8262 Compliance Test Results for the LMK5C33216
Application report for ITU-T G.8262 compliance test
Application note
ITU-T G.8262 Compliance Test Results for the LMK5C33216
Application report for ITU-T G.8262 compliance test
Featured products for PTP
Clocking solutions that enable synchronized interfacing between data converters and FPGAs
We designed our portfolio of high-performance radio-frequency phase-locked loops (PLLs) and synthesizers, JESD204-compliant high-frequency clock distribution products, and multifunctional jitter cleaners and synchronizers to meet clocking requirements for JESD204B and JESD204C applications.
- Generate phase synchronous clocks. Our devices include features such as system reference (SYSREF) generation, phase sync, output clock-phase adjustment, input-to-output zero-delay modes and SYSREF widowing to enable precise timing between gigahertz clocks and SYSREFs.
- Ultra-low noise. Our PLLs, equipped with multi-core VCOs, external VCO support and external phase-detector support, help meet the most stringent phase-noise requirements.
User guide
How to Phase Synchronize Multiple LMX2820 Devices
Explains the theory of phase synchronization with LMX2820, the limitations of phase synchronization, and demonstrates how to set up synchronization in a step-by-step guide
Application note
LMX1204 Multiplier Clock Distribution Drives Large Phased-Array Systems
Describes how to distribute a low phase-noise clock or local oscillator (LO) signal across many channels and also how to employ an integrated multiplier operating between 3.2- and 6.4-GHz output
Reference design
Multi-channel RF transceiver, low-noise clocking reference design for radar and EW applications
This reference design demonstrates LMX2820 and LMK04832-based low-noise JESD204B-compliant clocks and provides multiple AFE7950s.
PCIe clocks and timing: generations 1 to 6
PCIe applications have expanded far beyond the original PC market to include data center, automotive, and communication network applications. We have a full PCIe product portfolio including clock generators, fanout buffers, oscillators, and clock muxes. Our devices support all PCIe clocking architectures including common clocks with SSC, SRNS, and SRIS.
- System benefits. Devices include features such as glitch-free control logic, fail-safe inputs, low propagation delay, tightly controlled output-to-output skew, and high-performance frequency accuracy and PSNR.
- Ease of use. Our PCIe portfolio offers pin-to-pin compatible oscillators and buffers and the industry's first reference-less clock generator that come in small package sizes.
Application note
Clocking for PCIe Applications
The widespread use of PCIe and the need for increased data throughput requires clocking products. TI offers a broad portfolio of clock generator and clock buffer products that meet the most demanding PCIe Gen 6.0 compliance.
White paper
The Importance of Clocks in Data Centers
TI provides a complete portfolio that meets any data center clocking requirement, simplifies clock trees through greater integration, improves system performance with lower jitter and reduces the bill of materials (BOM) cost.
Featured products for PCIe applications
Discover featured applications
Wired networking
Improve signal integrity and reduce total solution cost for next-generation 112-G and 224-G PAM4 SerDes clocking with ultra-low jitter clocks enabled by TI's BAW technology
Wireless Infrastructure
Bulk acoustic wave-based network synchronizers, radio-frequency synthesizers and clock distribution have made TI clocking solutions popular in 4G and 5G networks, paving the way to 6G designs
Enterprise
Maximize system reliability and performance in enterprise systems using multisource, high-performance Peripheral Component Interconnect Express (PCIe) Gen 1 through Gen 6 and Ethernet clocking devices
Defense
Meet precise synchronization requirements and deliver low-noise systems using our clocking and radio-frequency synthesizer solutions
Space
Perform in the harshest radiation environments using TI's radiation-tolerant and radiation-hardened clocking and RF synthesizer solutions
Test equipment
Unlock new levels of performance, speed and precision in your test equipment by choosing TI's clocking and RF synthesizer solutions
Improve signal integrity and reduce total solution cost for next-generation 112-G and 224-G PAM4 SerDes clocking with ultra-low jitter clocks enabled by TI's BAW technology
TI's bulk acoustic wave (BAW) technology and broad clocking portfolio with excellent jitter performance enable TI to stand out as a leading clocks supplier.
- Ultra-low jitter (42-fs) clocks for 112G and 224G PAM-4 SerDes.
- Low-frequency XO, TCXO or OCXO, the elimination of an external low-dropout regulator requirement and an exceptional power-supply rejection ratio reduce total solution costs.
- IEEE 1588 Precision Time Protocol (PTP) synchronous Ethernet solution. Best-in-class jitter along with Class-D timing-accurate PTP software meets G8275.1 and G.8275.2 compliance.
Featured resources
END-EQUIPMENT / SUB-SYSTEM
PRODUCTS
- LMK5B33216 – 16-output, three DPLL and APLL, network synchronizer with integrated 2.5-GHz bulk-acoustic-wave VCO
- LMK03328 – Ultra-low jitter clock generator family with two independent PLLs
- LMK6P – Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency LVPECL oscillator
TECHNICAL RESOURCES
DESIGN TOOLS AND SIMULATION
- CLOCK-TREE-ARCHITECT – Clock tree architect programming software
- PSPICE-FOR-TI – PSpice® for TI design and simulation tool
SOFTWARE DEVELOPMENT
- TICSPRO-SW – Texas Instruments Clocks and Synthesizers (TICS) Pro Software
Bulk acoustic wave-based network synchronizers, radio-frequency synthesizers and clock distribution have made TI clocking solutions popular in 4G and 5G networks, paving the way to 6G designs
Our network synchronizer's hitless switching and holdover performance help you design reliable systems, while our ultra-low-jitter clocks simplify 5G designs.
- Integrated LDOs provide a <–75-dBc power-supply rejection ratio on supply rails.
- DC coupling and easy interface with analog front ends, with JEDEC JESD204B and JESD204C support.
- Institute of Electrical and Electronics Engineers 1588v2 Precision Time Protocol software provides full timing support; 1-PPS signal deviation <±5 ns; and partial timing support less than ±1 µs, with packet delay variations in excess of 230 µs.
Featured resources
END-EQUIPMENT / SUB-SYSTEM
REFERENCE DESIGNS
- TIDA-010230 – Multi-channel RF transceiver, low-noise clocking reference design for radar and EW applications
PRODUCTS
- LMK5C33216 – Ultra-low jitter clock synchronizer with JESD204B for wireless communications with BAW
- LMX2820 – 22.6-GHz wideband RF synthesizer with phase synchronization, JESD and <5-µs frequency calibration
- LMK00301 – 3-GHz, 10-output differential fanout buffer / level translator
TECHNICAL RESOURCES
- ITU-T G.8262 Compliance Test Results for the LMK5C33216 – Application note
SOFTWARE DEVELOPMENT
- TICSPRO-SW – Texas Instruments Clocks and Synthesizers (TICS) Pro Software
- PLLATINUMSIM-SW – Texas Instruments PLLatinum Simulator Tool
Maximize system reliability and performance in enterprise systems using multisource, high-performance Peripheral Component Interconnect Express (PCIe) Gen 1 through Gen 6 and Ethernet clocking devices
Our PCIe and Ethernet clocking portfolio includes bulk acoustic wave oscillators, fanout buffers, clock multiplexers and referenceless clock generators.
- Ultra-low jitter helps PCIe Gen 1 to Gen 6 compliance with greater noise margin.
- Low propagation delay enables multiple PCIe buffer cascading.
- Integrated LDO and a high peak signal-to-noise ratio simplify power-filtering circuits.
- Programmable output formats including low-power high speed current steering logic, low-voltage differential signaling, and 1.2- to 3.3-V low-voltage complementary metal-oxide semiconductor.
Featured resources
END-EQUIPMENT / SUB-SYSTEM
PRODUCTS
TECHNICAL RESOURCES
- BAW Oscillator Solutions for Network Interface Card – Application brief
Meet precise synchronization requirements and deliver low-noise systems using our clocking and radio-frequency synthesizer solutions
Our clocking products and radio-frequency phase-locked loops (PLLs) enable ultra-low-noise performance and synchronization features.
- High-performance PLLs, an external voltage-controlled oscillator (VCO) mode and an external phase detector input mode help meet stringent noise requirements.
- Multicore VCOs and calibration algorithms enable wideband coverage and fast frequency hopping.
- Phase synchronization and adjustability and input windowing features simplify multigigahertz clock synchronization in Joint Electron Device Engineering Council JESD204B and JESD204C systems.
Featured resources
END-EQUIPMENT / SUB-SYSTEM
REFERENCE DESIGNS
- TIDA-010230 – Multi-channel RF transceiver, low-noise clocking reference design for radar and EW applications
- LMX2594PSEVM – LMX2594 evaluation module for 15-GHz RF synthesizer with multiple-device phase synchronization
PRODUCTS
- LMX2820 – 22.6-GHz wideband RF synthesizer with phase synchronization, JESD and <5-µs frequency calibration
- LMX1204 – 12.8-GHz RF buffer, multiplier and divider with JESD204B/C SYSREF support and phase synchronization
- LMK5B33216 – 16-output, three DPLL and APLL, network synchronizer with integrated 2.5-GHz bulk-acoustic-wave VCO
TECHNICAL RESOURCES
- LMX2820 RF Synthesizer Phase Noise Improvement With Alternative Topologies (Rev. A) – Application note
- Getting the Most of Your Data Converter Clocking System Using LMX1204 – Application note
SOFTWARE DEVELOPMENT
- PLLATINUMSIM-SW – Texas Instruments PLLatinum Simulator Tool
- TICSPRO-SW – Texas Instruments Clocks and Synthesizers (TICS) Pro Software
Perform in the harshest radiation environments using TI's radiation-tolerant and radiation-hardened clocking and RF synthesizer solutions
Our high-performance and feature-rich clocking products help you deliver high bandwidth, with wide radio-frequency (RF) coverage in harsh radiation environments.
- Highly integrated monolithic clock generators and RF synthesizers help reduce size, weight and power in spaceborne applications.
- Design practices and process characteristics enable consistent, predictable behavior in harsh radiation environments.
- Access to detailed radiation reports covering various device modes along with 60 years of expertise in space products helps reduce time to launch.
Featured resources
END-EQUIPMENT / SUB-SYSTEM
REFERENCE DESIGNS
- TIDA-010191 – Space-grade multichannel JESD204B 15-GHz clocking reference design
PRODUCTS
- LMK04832-SEP – Radiation-tolerant, 30-krad, ultra-low-noise, 3.2-GHz 15-output JESD204C clock jitter cleaner
- LMX2615-SP – Space grade 40-MHz to 15-GHz wideband synthesizer with phase synchronization and JESD204B support
- LMK04832-SP – Radiation-hardened-assured (RHA), ultra-low-noise, 3.2-GHz, 15-output clock jitter cleaner
TECHNICAL RESOURCES
- Total Ionizing Dose and Single Event Effects Test Results of LMK04832-SP – More literature
- Why Component Integration Matters for Space-Based PLL Synthesizers – Technical article
SOFTWARE DEVELOPMENT
- PLLATINUMSIM-SW – Texas Instruments PLLatinum Simulator Tool
- TICSPRO-SW – Texas Instruments Clocks and Synthesizers (TICS) Pro Software
Unlock new levels of performance, speed and precision in your test equipment by choosing TI's clocking and RF synthesizer solutions
Our clocking products and radio-frequency (RF) phase-locked loops seamlessly reduce noise and design complexity, enabling applications from precision semiconductor and wireless communications testers to lab instruments.
- RF synthesizers equipped with calibration algorithms enable wideband frequency coverage and fast frequency hopping.
- Feature-rich products simplify phase synchronization for multichannel gigahertz sampling systems.
- Ultra-low-jitter clock buffers and clock generators enable high-speed interfaces from Peripheral Component Interconnect Express to Ethernet.
Featured resources
END-EQUIPMENT / SUB-SYSTEM
PRODUCTS
TECHNICAL RESOURCES
- Dramatically Improve Your Lock Time with VCO Instant Calibration – Application note
- LMX2820 RF Synthesizer Phase Noise Improvement With Alternative Topologies (Rev. A) – Application note
SOFTWARE DEVELOPMENT
- PLLATINUMSIM-SW – Texas Instruments PLLatinum Simulator Tool
- TICSPRO-SW – Texas Instruments Clocks and Synthesizers (TICS) Pro Software
Technical resources
Video series
TI Precision Labs - Clocks & Timing videos
Develop your clocks and timing expertise with our comprehensive curriculum of training videos that cover key topics from fundamental terminology and factors of system noise to more advanced design considerations.
Application note
Multi-Clock Synchronization
Learn how to synchronize multiple devices by either a divider reset, 0-delay, or combination of both methods.
Technical article
How to select an optimal clocking solution for your FPGA-based design
Learn more about the key factors in choosing a clocking solution for FPGA-based applications.