首頁 數據轉換器 類比轉數位轉換器 (ADC) 高速 ADC (≥10 MSPS)
首頁
數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)
新增

ADC12DL1500

現行

12 位元、雙 1.5GSPS 或單 3GSPS 類比轉數位轉換器 (LVDS 介面)

立即訂購
產品規格表

ADC12DL1500

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 1500, 3000 Resolution (Bits) 12 Number of input channels 1, 2 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2770 Architecture Folding Interpolating SNR (dB) 56.8 ENOB (bit) 9 SFDR (dB) 67 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1500, 3000 Resolution (Bits) 12 Number of input channels 1, 2 Interface type DDR LVDS, Parallel LVDS Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2770 Architecture Folding Interpolating SNR (dB) 56.8 ENOB (bit) 9 SFDR (dB) 67 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCBGA (ACF) 256 289 mm² 17 x 17
  • ADC core:
    • 12-Bit resolution
    • Up to 1GSPS, 3GSPS, 5GSPS in single-channel mode
    • Up to 500MSPS, 1.5GSPS, 2.5GSPS in dual-channel mode
  • Internal dither for low-magnitude, high-order harmonics
  • Low-latency LVDS interface:
    • Total latency: < 10ns
    • Up to 48 data pairs at 1.6Gbps
    • Four DDR data clocks
    • Strobe signals simplify synchronization
  • Noise floor (no input, VFS = 1VPP-DIFF):
    • Dual-channel mode: -143.5, -148, -149.8dBFS/Hz
    • Single-channel mode: -146.2, -150.3, -152.2dBFS/Hz
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 8GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19fs step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • Power consumption: 2.6, 2.8, 3W
  • ADC core:
    • 12-Bit resolution
    • Up to 1GSPS, 3GSPS, 5GSPS in single-channel mode
    • Up to 500MSPS, 1.5GSPS, 2.5GSPS in dual-channel mode
  • Internal dither for low-magnitude, high-order harmonics
  • Low-latency LVDS interface:
    • Total latency: < 10ns
    • Up to 48 data pairs at 1.6Gbps
    • Four DDR data clocks
    • Strobe signals simplify synchronization
  • Noise floor (no input, VFS = 1VPP-DIFF):
    • Dual-channel mode: -143.5, -148, -149.8dBFS/Hz
    • Single-channel mode: -146.2, -150.3, -152.2dBFS/Hz
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 8GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19fs step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • Power consumption: 2.6, 2.8, 3W

The ADC12DL500, ADC12DL1500 and ADC12DL2500 are a family of analog-to-digital converters (ADC) that can sample up to 500MSPS, 1.5GSPS, and 2.5GSPS in dual-channel mode and up to 1GSPS, 3GSPS, and 5GSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and sample rate (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications.

The devices uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing.

The ADC12DL500, ADC12DL1500 and ADC12DL2500 are a family of analog-to-digital converters (ADC) that can sample up to 500MSPS, 1.5GSPS, and 2.5GSPS in dual-channel mode and up to 1GSPS, 3GSPS, and 5GSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and sample rate (single-channel mode) allow development of flexible hardware that meets the needs of both high-channel count or wide instantaneous signal bandwidth applications.

The devices uses a low-latency, low-voltage differential signaling (LVDS) interface for latency sensitive applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four 12-bit data buses. The interface supports signaling rates of up to 1.6Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device synchronization is further eased by innovative synchronization features such as noiseless aperture delay (TAD) adjustment and SYSREF windowing.
open-in-new 尋找其它 高速 ADC (≥10 MSPS)
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋後再試一次。
檢視所有 1
類型 名稱 日期
* Data sheet ADC12DLx500 0.5, 1.5, 2.5GSPS Dual-Channel or 1, 3, 5GSPS Single-Channel,12-Bit Analog-to-Digital Converters (ADC) With LVDS Interface datasheet PDF | HTML 2024年 1月 31日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ADC12DL2500EVM — ADC12DL2500 評估模組

ADC12DL2500 評估模組 (EVM) 用於評估 ADC12DL2500，這是一款具有 LVDS 介面的 12 位元、雙 2.5GSPS 或單 5GSPS、射頻取樣類比轉數位轉換器 (ADC)。EVM 具備單端 AC 耦合類比輸入、板載 ADC 時鐘產生及電源調節電路。 EVM 設計為直接連接 TSW14DL3200EVM。透過高速資料轉換器專業級軟體 (DATACONVERTERPRO-SW) 分析工具提供額外支援。
使用指南: PDF | HTML
TI.com 無法提供
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
封裝 引腳 下載
FCBGA (ACF) 256 檢視選項
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中可靠性監測

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片